The microelectronics sector is at a critical juncture where rules established decades ago are beginning to falter. In this context, Huawei has presented a disruptive proposal called Tau ($ au$) Scaling Law, a new guiding principle that seeks to guide the evolution of semiconductors and global electronic systems, moving away from traditional paradigms.
This initiative, presented by He Tingbo at the International Symposium on Circuits and Systems (ISCAS), arises as a response to the exhaustion of Moore's Law. After more than fifty years of dominance, the geometric scaling of transistors It has encountered insurmountable physical barriers and ever-decreasing economic profitability, forcing the industry to seek alternative and sustainable routes.
A change of focus: from size to time
The essence of this new law consists of replacing the obsession with reducing physical size (geometric scaling) with time-based scaling ($ au$)The main objective is to systematically reduce the time constant to compress signal propagation delays, thus improving transistor density without relying exclusively on extreme miniaturization.
To materialize this concept, the company has developed the architecture LogicFoldingThis technology allows for breaking with traditional circuit design patterns, shortening critical wiring paths and reducing capacitive and resistive loads, resulting in a qualitative leap in performance and the energy efficiency of the components.
The deployment of this strategy is not merely theoretical, as it is applied within a framework of multi-level co-optimization which covers four fundamental areas:
- Device level: Parasitic resistances and capacitances are optimized to minimize the constant $au$ in the physical basis.
- Circuit level: The use of LogicFolding eliminates physical barriers in the design, enhancing circuit density.
- Chip level: A coordinated software and silicon design is implemented for a precise control of data flow and greater parallelism.
- System level: Through UnifiedBus, interconnection protocols are redefined to reduce communication latency in SuperPoDs systems.
Market impact and long-term goals
As for the practical application, Huawei has already designed and produced 381 chips based on this principle over the past six years. The next milestone will be the launch of the new Kirin processors, expected in the fall of 2026, which will be the first to integrate the LogicFolding architecture, promising a significant improvement in the power of mobile devices.
Looking to the future, the company has set an ambitious goal: by 2031, its high-end chips will reach a transistor density equivalent to 1,4 nmThe most relevant aspect of this announcement is that this advance would be possible without relying on extreme ultraviolet (EUV) lithography machines, tools to which the Chinese giant has restricted access due to international trade sanctions.
This path toward technological self-sufficiency not only seeks to mitigate external constraints, but also to offer competitive alternatives in the field of artificial intelligence. The growing demand for Ascend chips In China it is already a reality, serving as the basis for more than 80 extensive language models that seek to optimize home computing capacity.
Huawei's strategy is based on the conviction that real progress is only achieved through open collaboration with scientists and engineers from around the world. By proposing a new global standard, the company aims to lead a transition where time efficiency is key to sustaining the growth of advanced computing and consumer electronics.