The race for the next big leap in the semiconductor industry is narrowing and Samsung has decided to make a strong move.While much of the industry is still establishing 3nm and beginning to deploy 2nm, the South Korean giant has already outlined a very specific goal in its roadmap: to bring a process into production. 1 nm supported on transistors Forksheet.
This move isn't just a matter of technological marketing. It's about trying to compete head-to-head with TSMC and Intel in the first division of miniaturizationrelying on a transistor architecture different from what has been used until now. Samsung's strategy combines an ambitious timeline with a profound change in how silicon is organized internally.
A 1 nm node that seeks to push the physical limits
According to information coming from South Korea, the company is working with the goal of have the 1 nm process ready around 2031Before that, during this decade, it should complete an intense phase of research and development to determine whether the leap is industrially viable or remains a laboratory exercise.
When we talk about 1 nm in this context, it's not just about a smaller number on the technical specifications. We're talking about channel widths close to one nanometer, on the order of a few atomsThis puts Samsung very close to what is currently considered the practical limit of silicon-based CMOS technology. Each reduction in scale presents a greater challenge in materials control, current leakage, and process variations.
The South Koreans' plan is not part of an isolated movement, but rather part of a broader strategy. a phased offensive that combines the maturation of the 2 nm with the preparation of the 1nm node. In parallel with this development, Samsung is defining specific 2nm variants for specific customers and for its own products, from mobile SoCs to chips for data centers.
The key, both in 2nm and in the future 1nm, is to maximize density and efficiency without increasing production costs. This is where the Forksheet architecture comes into play, which aims to Utilizing every square millimeter of silicon while minimizing dead space between devices.
From GAA to Forksheet: a new step in transistor architecture
Until now, Samsung's big bet on advanced nodes has been on technology GAA (Gate-All-Around), commercially launched in its 3nm process. This approach consists of surrounding the transistor channel on all sides with the control gate, which significantly improves the control of electrical flow compared to traditional FinFETs.
However, the GAA architecture itself begins to show its limitations when attempts are made to scale it down even further. Simply taking the same idea to 1 nm doesn't provide all the necessary margin, so Samsung's plans include a different approach. Forksheet as a natural evolution of GAAThe concept of a gate surrounding the channel is not abandoned, but the way the transistors are distributed on the chip is reorganized.
The essence of the Forksheet is in introduce a kind of insulating “wall” between adjacent transistorsThis dielectric barrier allows the N and P structures to be placed much closer together without interfering with each other. The result, on paper, is a significant reduction in the space occupied by each logic cell.
Less distance between devices means higher density and, potentially, higher yield per area (PPA)By compressing the design, it is possible to integrate more logic, more cache, or more specialized units into the same chip size, which is key to continuing to improve performance without multiplying power consumption.
This approach comes at a cost: the manufacturing process becomes considerably more complex. Controlling the formation of that insulating wall with absolute precision, keeping the channels aligned, and ensuring that leaks don't occur is a challenge that demands pushing the limits of current lithography capabilities, including the EUV exposure in its most advanced variants.
Schedule, risks and the battle to get there first
Samsung's strategy has a technological component and, clearly, a positioning component. Historically, the company has sought gain visibility by being the first to reach certain milestones: was a pioneer in using EUV at 7 nm and also in introducing GAA at 3 nm, although the initial results were not always as solid as the market expected.
In the case of the 1nm node with transistors (Forksheet), the company is attempting something similar again. Available information suggests an R&D phase that should be completed by 2030, to leave the door open to initial production around 2031. This is not a very different timeframe from that attributed to other players in the sector, so the real advantage will not be measured solely in dates.
The real test will be whether that theoretical advantage of the Forksheet architecture translates to manufacturing lines with acceptable yields and controlled costsIn previous generations, yield issues and process tuning have made the difference between a successful launch and a node that is barely used in commercial products.
Samsung already experienced that situation firsthand with its first 3nm process, where The rates of valid chips were not as expected at the beginning.The accumulated experience can now be used to refine the problems sooner, but it does not prevent the jump to 1 nm from opening a new can of worms in terms of variability and defects.
Meanwhile, the company continues to hold second place in the foundry market by volume, far behind TSMC, which maintains a share exceeding 70% of the sectorThis difference in scale means that every decision regarding investment and timelines carries even more weight in Samsung's roadmap.
The role of 2nm and Samsung's current situation
While the 1nm node is slowly being developed, the company has another immediate front to contend with: consolidate its 2 nm offeringThis process will, in practice, determine the performance of chips that reach the European and global market in the short and medium term, both in mobile phones and other devices.
Samsung's 2nm process is based on the same GAA philosophy, but with improvements to reduce power consumption and increase performance compared to 3nm. On this point, the latest public data and leaks suggest that There is still room for improvement in efficiencyespecially when comparing some of our own SoCs with rivals manufactured in equivalent nodes from other foundries.
In synthetic tests, certain chips designed by Samsung itself have shown high peak consumption under heavy loadThis impacts device battery life and operating temperature. Compared to alternatives based on advanced processes from other manufacturers, significant differences in usage time have been observed.
These results underscore that, before considering a mass deployment of 1nm, the company needs fine-tune its 2nm technology and stabilize yieldsThe alternative would be to build the next step on a still unstable foundation, with the risk of dragging efficiency and cost problems to the new node.
Even with these difficulties, the development of 1nm is seen as a long-term investment. If Samsung manages to close the efficiency and performance gap at 2nm, It could reach the 1 nm window with a much stronger positioncapable of attracting European and global customers who today depend almost exclusively on TSMC.
Potential impact on the market and on devices
Beyond the nanometer figures and the technical debate, what matters to the end user is what this can change in their daily lives. A well-executed 1nm process would allow Smaller, more powerful, and lower-consumption chipsThis would affect virtually all types of electronic devices.
In the realm of smartphones, this would translate to mobile phones with higher sustained performance and better battery lifewith fewer overheating issues when gaming or running demanding tasks. In laptops and desktops, the improvement could translate into thinner designs, less reliant on bulky cooling systems.
There would also be an impact on sectors such as IoT, automotive, and cloud computing. The possibility of integrate more logic and memory into the same space It opens the door to smarter sensors, vehicles with more advanced assistance systems, and data centers capable of processing more information per watt.
For Europe and Spain, where strategic autonomy in semiconductors has become a recurring theme, the evolution of nodes like the 1 nm node has a different interpretation: define which suppliers will be able to manufacture the most advanced chips when the major projects promoted by the EU Chips Act and other public support programs come into effect.
If Samsung manages to consolidate its Forksheet technology and offer a competitive alternative to TSMC in these nodes, European chip designers will have more room to maneuver when choosing where to produce their high-performance solutions, from supercomputing processors to AI accelerators.
For now, Samsung's plan rests on a combination of technological ambition and the need to differentiate itself from its rivals. The leap to the 1nm chips with transistors Forksheet It is presented as the next great frontier, but its success will depend on more than just being first: it will be necessary to balance performance, costs and reliability so that this "dream semiconductor" ends up powering the devices we will see on the European market in the next decade.