The idea that anyone can order custom silicon without breaking the bank no longer sounds like science fiction: wafer.space offers a way to make your own chips at a cost of $7 per die Taking advantage of joint runs on a mature and documented technology. The approach is reminiscent of what was once meant to make PCBs cheaper, but applied to the integrated circuit field.
In this analysis, we explain in detail how the initiative works, what the first run on the GF180MCU platform offers, what you need to upload your design, and what role RISC-V can play if you want to integrate an open source processor into your chip. We also put this movement into context in the face of the race to manufacture semiconductors for AI., with multi-million dollar projects such as those associated with OpenAI, TSMC and large international funds.
What wafer.space is proposing and why is there talk of $7 per diem?
wafer.space has opened its first joint manufacturing run on GF180MCU technology, with a purchase deadline of November 28, 2025. The official description compares it to an “OSH Park for silicon.”: You share the wafer with others, optimize costs, and receive your manufactured dies at a price well below a traditional private run.
The “$7 per die” hook encapsulates the ambition: to bring silicon closer to developers, labs, and small businesses that previously could only prototype on FPGAs. The key is in the shuttle model or joint run, where multiple designs are panelized on a single wafer to spread mask and process costs.
The offer is organized through a CrowdSupply campaign page for “GF180MCU Run 1,” where the reservation and purchase are made. You can check it out at https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/, the entry point to find out about quotas, specifications and the schedule.
For those interested, the GF180MCU is a 180nm process with publicly documented materials and libraries; its open PDK is available at https://gf180mcu-pdk.readthedocs.io/. The availability of standardized documentation and cells makes a design flow based on open source tools viable., further reducing the barrier to entry for small teams.
How the GF180MCU co-run works
The mechanism is simple: you provide a design of up to 20 mm2 for GF180MCU technology and once the wafer is manufactured, you receive 1.000 pieces corresponding to your block. This surface area, 20 mm2, set the area budget for logic, memory, pads, and any IP you integrate; is a generous limit for controllers, specific ASICs, or custom microcontrollers with accelerators.
An interesting detail is that you don't have to start from scratch. You can use an existing template or build the chip completely from scratch., based on your experience, timeframe, and ambition. This accelerates time-to-silicon for those who want to iterate quickly without taking risks the first time.
In terms of tools, the initiative doesn't lock you into a single ecosystem: open source suites like LibreLane, Magic, or KLayout are supported, as well as proprietary workflows if you're already part of an enterprise environment. Tool flexibility avoids friction and allows the flow to be adapted to the capabilities of each team., whether you prefer community scripts and tools or commercial EDA licenses.
Another advantage is that no pad ring or dedicated management CPU is required for delivery. This simplifies the logical packaging of the design and avoids ties to specific platforms., something very useful when the objective is to incorporate the minimum essential to validate the idea in silicon.
The timeline is clear: the purchase deadline is November 28, 2025, a sufficiently long window to prepare the netlist, verify, and physically close the contract. This milestone marks the completion of inclusion in the shared wafer.; from then on, manufacturing and testing follow the foundry's schedule.
Design Tools: From KLayout and Magic to Open Flows
The GF180MCU PDK, available in the foundry's public documentation, provides a range of design options. Tools like Magic and KLayout are benchmarks for layout and visual review., with very active communities and abundant examples of use in mature processes.
For synthesis automation and place & route, the reference to LibreLane points to a flow of integrated open tools, with scripts to bring from RTL to GDS. This approach is attractive if you want reproducibility and CI pipelines.: The same script that runs on your laptop can run on a server and produce the same result.
If you already work with commercial EDA, you're not limited: you can use your proprietary workflow for formal verification, timing, and physical closure, exporting final GDS compatible with the GF180MCU. The PDK's compatibility with market tools ensures that companies do not have to retrain teams. nor remake libraries from scratch.
A practical tip for small teams: start with a verified minimalist template or SoC, add your IP, and validate with aggressive testbenches. Shuttle costs are competitive, but each spin of silicon still requires verification discipline.; investing time in testing will save you trouble after the tape-out.
RISC-V as an architecture ready to integrate
If your chip requires an embedded processor, RISC-V is the natural candidate. It's a modular, extensible, license-free instruction set architecture, born in Berkeley and now adopted in a wide range of products. Examples range from $0,10 CH32V003 microcontrollers to pan-European supercomputing initiatives., through to 64-core workstations at 2 GHz in the professional field.
RISC-V fits very well in two useful scenarios for this type of runs: as a soft core in an FPGA for rapid prototyping, and as an embedded CPU in your 180nm SoC for control and general tasks. Even as a high-performance software virtual machine, RISC-V has demonstrated versatility., allowing you to validate your software stack before having the real silicon.
Additionally, its open ecosystem makes it easy to reuse toolchains, debuggers, and RTOS without license dependencies. For more information and resources, the official website is https://riscv.org, a good starting point for choosing a core, extensions and software support.
Dates, quantities, area and requirements: the essentials
To summarize the offer: You have until November 28, 2025, to make your purchase and secure your slot on the shared GF180MCU wafer. The design can take up to 20 mm2 and after manufacturing, you will receive 1.000 units, an ideal amount for validation, internal development kits or first demos for clients.
The methodology does not impose a fixed pad ring or management controller, giving you the freedom to prioritize your logic or IP. You can start with an existing template to minimize risks or build everything custom if your team already has experience. in physical closings and verification.
In the pipeline, they combine open tools like LibreLane, Magic, and KLayout with proprietary utilities well, as long as the result is a GDS and verification consistent with the 180nm PDK. The public documentation for the GF180MCU PDK at https://gf180mcu-pdk.readthedocs.io/ is key to clearing up any doubts. on design rules, layers, libraries and electrical parameters.
And yes, the message running through the community—“$7 a die”—is best understood in the context of a joint run: It's about democratizing access to silicon by assuming you share wafer and costs with other designs., a proven model that brings the collaborative philosophy that has already been successful in PCB manufacturing to the chip.
The industrial context: from an “OSH Park for silicon” to the AI chip craze
While initiatives like wafer.space are pushing silicon access horizontally, at the other end of the spectrum, mountains of capital are being moved to secure next-generation, AI-focused manufacturing capacity. According to multiple reports, OpenAI CEO Sam Altman has launched a fundraiser to build a foundry network and secure custom chips for his models..
In one of the disclosed proposals, the main interested parties would be G42 (an AI conglomerate from Abu Dhabi) and SoftBank Group (owner of ARM), with an estimated investment of between $8.000 billion and $10.000 billion to deploy customized capabilities. In parallel, talks have been reported to raise between five and seven billion dollars. intended to dramatically expand the global AI-focused semiconductor infrastructure.
These dizzying figures contrast with the spirit of an accessible shuttle, but they draw the same backdrop: AI computing demand is limited by GPU shortages, essential for training and running large models due to their ability to perform matrix multiplications in parallel.
In this scenario, TSMC—the world's largest independent foundry—is an industrial pivot on which companies like Nvidia, Apple, Intel, and AMD depend to produce SoCs, CPUs, and GPUs. The participation of TSMC and international investors such as the UAE underlines the strategic nature of manufacturing, with obvious geopolitical and regulatory implications.
The United States, aware of the importance of semiconductors in the digital economy and national security, has stepped up domestic support: The Biden administration has announced $5.000 billion for R&D in semiconductor technologies. and has increased scrutiny of foreign investments in critical sectors. In parallel, TSMC is investing $40.000 billion in its Arizona plant, one of the largest foreign capital investments in the country's history.
For those who will be leveraging the GF180MCU, this macro trend matters because it stabilizes supply chains, shortens lead times, and promotes the standardization of open PDKs. The existence of a “low cost” prototyping lane does not compete with the “high end” of 5 nm and 3 nm, but both worlds feed back and strengthen the ecosystem.
Practical tips for arriving on time for the tape-out
Organize the project into two lanes: specification and verification on one hand, and physical closure on the other. Freeze the instruction set (if using RISC-V) and define interfaces from the beginning, to avoid last minute changes that complicate placement and routes.
Reuse proven IP where it makes sense: UART, SPI, I2C, timers, and GPIO are often available in open repositories. Dedicate your resources to the differentiator (accelerator, filter, DSP, encryption, etc.), and don't reinvent the wheel on basic peripherals.
Automate everything you can with scripts: synthesis, P&R, DRC, LVS, and GDS generation. A reproducible pipeline reduces human error and accelerates iterations. when rule violations or timing issues arise.
In post-silicon validation, plan your bring-up now: what package you'll use, how it's powered, what test pins you'll need, and what minimum firmware it will load the first time. The clearer your lab plan is, the less time you'll waste when your 1.000 pieces arrive..
The wafer.space movement brings silicon to teams of all sizes, and it does so with clear rules: an area of 20 mm2, 1.000 units and a deadline of November 28, 2025With an open PDK like the GF180MCU and accessible tools (LibreLane, Magic, KLayout, or proprietary workflows), the door is open for many designs currently in FPGAs to jump into the ASIC world. Meanwhile, at the other end of the spectrum, AI megaprojects and geopolitical investment in semiconductors are pushing the industry toward more capacity and better processes. Between the two extremes, a bridge is being built that allows for innovation from the bottom up without losing sight of the wave coming from above.