If you work with microcontrollers, FPGAs or serial buses, you're probably familiar with that chaos of cables and USB dongles taking up half the table. ESP32JTAG arrives to bring order: a single compact and wireless unit that combines JTAG/SWD debugging, a 16-channel logic analyzer at 250 MHz, a UART console and FPGA configuration, all accessible from the browser.
What's interesting is not only that it brings together key tools, but that They can all work at the same timeYou can debug an MCU, program an FPGA, analyze signals, and open a web terminal simultaneously, from a laptop, tablet, or even your mobile phone. With its integrated web server, there are no drivers to install. connect via Wi-FiEnter the interface and get to work.
What is ESP32JTAG and why is it of interest?
ESP32JTAG is an EZ32 proposal that is defined as a Swiss Army knife for embedded engineersThe device integrates on-chip debugging functions for MCUs (JTAG/SWD), development support for FPGAs (including XVC for Vivado), a high-performance logic analyzer, and a web-accessible UART terminal, all in a tiny form factor that can be left connected to the system under test.
Compared to traditional tools like ST-Link or basic USB JTAG adapters, The qualitative leap lies in flexibilityIt's wireless, multipurpose, and geared towards modern workflows with VSCode, PlatformIO, STM32CubeIDE, Arduino IDE, or Vivado. Furthermore, it's open hardware and runs open software, with published schematics, BOMs, and firmware to facilitate auditing, customization, and community improvement.
Architecture and main components
At the heart of the device is an Espressif ESP32-S3 module (see ESP32 Agent Dev Kit guide) with dual-core CPU (Xtensa LX7) up to 266 MHz, accompanied by 16 MB of flash and 8 MB of PSRAM to handle lossless debug traffic, web UI, protocols and logic analyzer buffers.
The second pillar is a small FPGA with a few 5k logic gates and 1 Mbit of RAM, completely controlled from the ESP32. This programmable logic allows switching port functions, implementing high-speed signal bridges, and sustaining analyzer sampling without throttling the main CPU.
Wireless connectivity depends on the review: some sources mention Wi‑Fi 6 and Bluetooth 5.0While others point to 2,4 GHz 802.11 b/g/n (Wi-Fi 4) and BLE 5.0. In any case, the approach is to operate wirelessly through a resident web interface (on FreeRTOS and ESP-IDF) that exposes configuration, OTA updates, documentation and tools.
The front includes a 1,83″ LCD screen to display IP, Wi-Fi status and system data, which is very useful when the equipment is "hooked" from the device under test and you need to locate it on the network at a glance.
In terms of physical format, the PCB is around 33 × 40 × 5 mm (interchangeable figures such as 40 × 33 × 5 mm according to the datasheet), it is powered by USB-C and offers four configurable four-wire ports where the JTAG/SWD, UART and logic analyzer modes are located, in addition to target voltage monitor and reset control.
Powerful, bottleneck-free MCU debugger
The debugging aspect of MCUs goes beyond the basics: It works with OpenOCD, GDBServer, Blackmagic Probe, and CMSIS-DAPTherefore, it integrates seamlessly with the most common IDEs (VSCode, STM32CubeIDE, Arduino IDE, PlatformIO…).
Compared to economical probes like ST-Link (which are usually mounted ARM at 72 MHz with 128 KB of flash and 24 KB of RAMThe ESP32-S3 at 266 MHz with 16 MB of flash and 8 MB of PSRAM is in a different league. This resource margin reduces the likelihood of debug data loss and allows for demanding sessions to be sustained while other functions run in parallel.
The combination of CPU, memory, and FPGA results in a smoother workflow: Fewer blocks, less waiting, and the ability to maintain breakpoints, memory inspection and logging without affecting the analyzer or web terminal.
Logic analyzer: 16 channels at 250 MHz
One of the claims is its logic analyzer of 16 channels at 250 MHzThis figure surpasses that of more expensive, single-purpose analyzers. This opens the door to sampling buses like high-speed SPI, capturing narrow events, and timing tight intervals without additional equipment.
The analyzer's web interface allows you to configure channels, take screenshots from the browser and review waveforms without installing desktop software. It's ideal for validating protocols, checking latencies, or hunting for glitches while you continue debugging firmware.
Web Interface for the Logic Analyzer
From the web panel you can adjust basic thresholds, times and triggers, as well as download screenshots for further analysis. The practical advantage is that you don't depend on host drivers or proprietary licenses.
Wireless and driverless operation
The integrated HTTP server eliminates the need to install packages: Turn it on, connect via Wi-Fi, and enter the UIThere you will find system settings, firmware updates, access to documentation and utilities (WebUART, analyzer, port configuration…).
In terms of connectivity, both Wi-Fi 6 and 2,4 GHz 802.11 b/g/n (Wi-Fi 4) are cited depending on the source and hardware iteration, always with Bluetooth 5.0 BLEFor cables, there's the USB-C which provides power and programming when needed.
WebTerminal
The browser-accessible UART console replaces many sessions of serial monitor Traditional. Without additional cables or virtual emulators, you can view logs, send commands, and permanently attach the tool to the target device.
FPGA support and workflows
ESP32JTAG also covers the FPGA side: it offers JTAG for programming and debugging, and is compatible with openFPGALoader and with XVC (Xilinx Virtual Cable) for integration with Vivado. This allows for the creation of hybrid MCU+FPGA workflows from a single device.
VSCode & Vivado – debug the MCU while iterating the FPGA
A typical scenario: while you iterate on the FPGA logic with Vivado via XVC, you keep the MCU under OpenOCD or BlackmagicAnd if you need to correlate events, you fire the logic analyzer to see what has happened on the critical lines.
Supported modes and I/O
In summary, modes and ports: JTAG/SWD debugging for MCUs (OpenOCD, Blackmagic Probe, CMSIS-DAP), JTAG for FPGA with openFPGALoader and XVCUART with WebUART/WebTerminal and 16-channel logic analyzer. It also monitors target voltage and allows reset control.
The four four-wire connectors are assigned to different roles as needed, with the FPGA taking over It multiplexes and sustains high-speed signals when needed. The design aims to simplify cabling and reduce the number of adapters on the console.
Open Inside: Hardware and Firmware
The project philosophy is open: schematics, PCBs, and BOMs will be published before production closes, and the The firmware is based on ESP-IDF and FreeRTOS., integrating pieces such as openocd-on-esp32, blackmagic-debug, CMSIS-DAP (DAPLink) and openFPGALoader.
In addition to the documentation on the device itself, there will be quick start guides in PDF format. video tutorials in preparation and a community channel (Discord and GitHub) for tracking issues and contributions.
Comparisons and practical performance
Compared to a classic ST-Link or Saleae-type analyzers, this proposal stands out for combining several functions with more ample hardware resourcesThis extra CPU, RAM, and FPGA support helps prevent capture drops, interface lockups, or packet loss during extended sessions.
Also important is the portabilityBeing small and powered by USB-C, it can be left integrated into the test bench or inside the casing of a prototype, with the added benefit of the screen to locate it on the network without connecting a host.
Hardware status, manufacturing, and packaging
The team has undergone hardware revision v1.3 and is working on v1.4, focused on improvements RF Wi-Fi, the casing and surface finish details. The idea is that v1.4 will be very close to the production unit.
Manufacturing will be handled by a PCB assembly house with experience in ESP32-based products. All boards will be They will test its functionality (wireless connectivity, I/O validation and LCD verification) before packaging.
The packaging will follow the consumer electronics standard: retail box with protective insertsThe main unit is packaged in an antistatic bag, and accessories are packaged in polybags. Shipments will be routed through Mouser's warehouse for worldwide distribution.
Certifications, component availability, and firmware maturity
In compliance and regulatory matters, it is expected FCC certification first, followed by CE and UKCA. Using a pre-certified ESP32-S3 module speeds up part of the process, although final certification of the complete product may introduce delays.
Regarding supplies, the choice of an ESP32-S3 and standard components It aims to mitigate risks related to global availability. At the software level, the core functions are operational, with testing and documentation being expanded; being open source, the community can help polish bugs and add features quickly.
Price, campaign and logistics
The ESP32JTAG is available for pre-order at Crowd Supply for $139with free shipping to the US and $12 to the rest of the world. The campaign exceeded its funding goal and will remain open until December 4, 2025, with deliveries expected to begin on February 14, 2026.
Logistics are handled through Mouser's network, which makes it easier tracking and reliability in global shipments. Order fulfillment and management are in line with your usual platform service.
Web interface: configuration, OTA and integrated documentation
The embedded UI offers system configuration, port mapping, network options, and access to OTA firmware updateIt also centralizes documentation so you don't depend on local manuals.
From the browser you can switch between the web terminal, the signal analyzer, status panels, and areas of diagnosis with internal metrics, which speeds up problem solving without jumping between applications.
Notes on connectivity: Wi-Fi and Bluetooth
According to various sources, Wi-Fi connectivity can refer to 802.11 b/g/n (Wi-Fi 4) or Wi ‑ Fi 6 In some iterations. In all cases, Bluetooth 5.0 BLE is mentioned. Beyond wireless, there is always the USB-C for power and, when applicable, programming.
Espressif documentation: OpenOCD and GDB in the ESP32 ecosystem
If you work in ESP-IDF environments, you'll be familiar with the official Espressif guide for installing OpenOCD and debugging with GDB. It explains how they relate to each other. xtensa‑esp32‑elf‑gdbOpenOCD and the JTAG interface for debugging, as well as the compilation, application loading and monitoring part.
When choosing a JTAG adapter, they recommend level compatibility (typically 3,3V on the ESP32), and note that the standard ESP32 JTAG port does not include TRST. The minimum signaling required for linking is TDI, TDO, TCK, TMS and GNDwith a possible Vtar line to fix voltage and optional SRST against CH_PD. They also warn that ESP32 does not support SWD, although ESP32JTAG does provide SWD for other MCU families.
During OpenOCD installation, it is advisable to verify that the ESP-IDF environment is properly loaded and that the variable OPENOCD_SCRIPTS This refers to the configuration scripts. If there are permission errors on Linux/macOS, the permission delegation should be reviewed according to the package's README file.
To start OpenOCD with a specific board, the following steps are taken: configuration files appropriate (the path is usually found in build/project_description.json under the debug_arguments_openocd field). If you get “Can't find board/…cfg” messages, check OPENOCD_SCRIPTS and make sure the file actually exists where indicated.
The guide also describes JTAG loading options using the command program_esp (file, offset, verify, reset, exit, compress, encrypt, no_clock_boost, restore_clock) and recommends trying first from the command line with GDB before moving to IDEs like Eclipse or VSCode.
In debugging, examples of code navigation, call stack, and WirelessBreakpoints (including conditionals), stepping, memory reading/writing, and variable observation are all covered. Binary paths (src/openocd) and script configurations for each operating system are detailed for compiling OpenOCD from source.
Alternatives, ecosystem and market context
There are related tools that complement or overlap functions: for example, WiSer for wireless P2P links, or USB-Cereal for testing devices with USB-C. The hardware similarity between ESP32JTAG and the LILYGO T-FPGA board (ESP32-S3 + FPGA GW1N) has also been noted, although the FPGA brand in ESP32JTAG is not officially confirmed.
As for external debuggers, the well-known ST-Link for STM32 or the ESP-Prog Espressif's JTAG lines connect to the ESP32, and in logic analyzers, Saleae-style models are used. The key difference is that ESP32JTAG handles several functions simultaneously and does so without a USB cable to the host.
If you look at online storefronts, there is no shortage of comparison tools and forms like "Have you seen a lower price?". Many stores They use these surveys to keep their rates competitive, although they can't always match all the offers they receive.
Highlighted technical specifications
- Processor: Dual-core ESP32-S3 up to 266 MHz
- Memory: 16 MB Flash, 8 MB PSRAM
- Connectivity: Wi-Fi (depending on source, Wi-Fi 4 or Wi-Fi 6), Bluetooth 5.0, USB-C
- Display: 1,83″ LCD for IP, Wi-Fi status and system info
- FPGA: ~5k logic gates, 1 Mbit RAM, configurable from the ESP32
- I / O: Four configurable 4-wire ports
- System: FreeRTOS on ESP-IDF
- Dimensions 33 × 40 × 5 mm (plate)
- Supported modes: MCU JTAG/SWD (OpenOCD, Blackmagic, CMSIS-DAP), JTAG for FPGA (openFPGALoader, XVC/Vivado), UART with WebUART, 16ch logic analyzer, voltage monitor and reset
- Distribution: Mouser worldwide; packaged with anti-static bag and protective materials
Documentation, support and roadmap
EZ32 publishes a web panel with user guides and updates, and works on a Quick-start in PDF and example videos (STM32, Raspberry Pi Pico, and ESP32). The campaign also features comparisons with other tools and news about certifications and production.
For community support, a Discord and a GitHub repository for reporting issues. They have also promised to release more open-source hardware materials (yet to be specified).
