Intel has presented Clearwater Forest, the new generation of processors Xeon 6+ for data centers that debut the node Intel 18A and an ambitious 3D design. The proposal unites process, packaging, and system architecture with the goal of increasing compute density and performance per watt without changing the foundation of the x86 ecosystem.
This family prioritizes efficiency and scalability with Darkmont cores server-oriented, large shared cache capacity, and distributed memory controllers. Thanks to packaging Foveros Direct 3D With the EMIB interconnection, the chip increases the internal bandwidth and enables configurations with up to 288 E-cores per socket for cloud-native and telecommunications loads.
3D design and Intel 18A node on Xeon 6+
The leap from manufacturing to Intel 18A It incorporates two pillars: Ribbon FET (gate-all-around transistors) and PowerVia (back-side feeding). The former allows for more efficient switching by surrounding the silicon wafers, while the latter reduces congestion and losses by separating power and signals, with clear benefits in density and consumption.
The key to packaging is Foveros Direct 3D, which stacks computing tiles directly onto the bases with copper-to-copper joints of approximately 9 µm, minimizing the resistance and energy cost of communication (around 0,05 pJ/bit). This approach enables fine-grained block scaling and heterogeneous component integration.
Combined with interconnection EMIB, the result is an internal subsystem with up to 1,9x bandwidth compared to the previous generation, capable of sustaining a higher number of cores and more I/O traffic without increasing latency or consumption.
To optimize costs and performance, Clearwater Forest mix processes: The I/O tiles They are manufactured in Intel 7, the base tiles on Intel 3 and the compute tiles on Intel 18A. This combination allows the most advanced node to be balanced where it contributes the most, while maintaining compatibility and maturity in the rest of the blocks.
Darkmont E-cores, Cache and Memory
The heart of Clearwater Forest is the Darkmont E-cores, designed to maximize performance per watt in the server. Compared to the previous generation, they incorporate improvements in the branch predictor, higher decoding capacity, more execution ports and the double vector computation; Intel quantifies an increase of ~17% in CPI opposite Crestmont.
Architecture multiplies density by organizing up to 288 E-cores per socket in compact modules. This philosophy favors the consolidation of microservices and containers, where a high number of efficient threads reduces operating costs and improves utilization resources per rack.
To hold such a number of threads, the base tiles integrate memory and cache: there are 192 MB of L3 per base (total 576 MB per CPU) and up to 288MB L2 distributed across the cluster. In addition, L2 bandwidth is doubled, with direct effects on latency and throughput of intensive processes.
In memory, the controller is distributed across the bases with 12 DDR5 channels capable of reaching up to 8000 MT/sThis configuration increases data feed to the E-cores, reduces bottlenecks and allows instances to be scaled with higher capacity and frequency of DRAM.
Interconnection, I/O, and Performance in Data Centers
The modular design integrates 12 compute tiles (Intel 18A) stacked on top 3 base tiles (Intel 3), joined by EMIB. The I/O tiles reuse the Granite Rapids base on Intel 7, bringing mature connectivity and already validated accelerators for production environments.
- Platform: configurations 1S/2S and TDP per CPU of 300 to 500 W.
- Interconnections: to 96 PCIe 5.0, 64 CXL 2.0 and to 6 UPI 2.0 links at 24 GT/s.
- Accelerators: to 16 integrated (4 QuickAssist, 4 Dynamic Load Balancer, 4 Data Streaming Accelerator and 4 In-Memory Analytics Accelerator).
- Security and management: intel sgx, Intel TDX, energy telemetry with Intel AET y Turbo Rate Limiter.
In performance, the company notes improvements of up to 1,9× compared to previous Xeon solutions based on E-cores, along with an increase in 23% in overall energy efficiency. In modernizations of older platforms, ratios of 8:1 consolidation, which helps reduce operating costs and consumption.
Intel has also shown impacts on infrastructure as a reduction of physical space up to 71% and savings of hundreds of kW In upgrade cases, figures aligned with the focus on density, large-scale management and integrated security for clouds and 5G networks.
Clearwater Forest is scheduled for commercial availability 2026. Meanwhile, the x86 ecosystem and OEM/CSP partners can prepare for transitions by leveraging the combination of Intel 18A, packaged 3D Foveros, faster DDR5 memory and a portfolio of accelerators that make it easy to optimize network loads, storage and memory analytics.
Xeon 6+ Clearwater Forest unites cutting-edge process, 3d architecture y Darkmont cores To increase the density per socket, expand the shared cache up to 576 MB, offer 12 DDR5 channels and first-class I/O (up to 96 PCIe 5.0), with a focus on enterprise deployments seeking performance per watt and scalability.
