Renesas is one of the numerous companies that is a member of RISC-V International, which already has a membership full of important corporations such as Intel, AMD, NVIDIA, Western Digital, Infineon, and a very long etc. Well, all these companies are there out of interest in following the ISA, for future chips based on it.
And that has been the example that Renesas has followed, designing a new CPU based on the 32-bit RISC-V ISA (RV32) and that has achieved a historic milestone, being the first of these features to achieve a score of 3.27 CoreMark/Mhz, which means more than remarkable performance.
What is CoreMark/Mhz
CoreMark/MHz is a metric used to measure the performance of a processor or processor core in terms of the number of CoreMark operations it can perform per Megahertz (MHz) of clock frequency. CoreMark is a benchmark developed by the Embedded Microprocessor Benchmark Consortium (EEMBC) and is used to evaluate the performance of processor cores in embedded and embedded systems.
In essence, CoreMark/MHz provides a relative measure of the processing efficiency of a core, allowing comparisons between different processor architectures and designs. The higher the CoreMark/MHz value, the more efficient the core will be in performing processing operations.
It is important to note that CoreMark is a synthetic benchmark designed to evaluate performance in specific applications, and results may not fully reflect performance in real-world applications. Additionally, different applications and workloads can affect performance differently, so it's crucial to consider multiple metrics and usage scenarios when evaluating a processor's performance.
First to reach 3.27 CoreMark/MHz
As I mentioned, Renesas has announced that it has designed a RISC-V CPU core, its first core based on this ISA. Is a 32-bit CPU, that is, with the RV32 instruction set. This CPU core is compatible with Renesas' e2 studio integrated development environment (IDE) and is compatible with other third-party IDEs for RISC-V microcontrollers, making things easier for developers.
According to Renesas, the CPU has achieved a performance of 3.27 CoreMark/MHz, surpassing similar RISC-V architectures in this category, and also other cores with other different architectures. However, given the topic of this blog, we are especially excited that it was a RISC-V core, since it is an open ISA, is rapidly gaining popularity in the semiconductor industry, and many microcontroller vendors have formed investment alliances joint venture to accelerate the development of its RISC-V products.
Previously, Renesas launched two CPUs developed by Andes Technology Corp, as is the case of the R9A02G020, a simple microcontroller for specific applications (ASSP or Application-Specific Standard Products) for motor control, and the R9A06G150, an ASSP microcontroller for voice interfaces, both based on RISC-V as well, but It was not designed by herself and it was about the MCU.
In addition to that, now Renesas introduces this family RZ/Five, a family of 64-bit RISC-V microprocessors capable of running Linux, and the RH850/U2B, a System on Chip (SoC) for automobiles. This complements the company's product inventory based on RISC-V.
Renesas RISC-V CPU Specifications
Technical specifications Of this Renesas RISC-V CPU, the following should be highlighted:
- The new Renesas CPU based on RISC-V is versatile, for various applications, and not as limited as in other cases. For example, it can be used in both MCUs, SoCs, ASICs, AASPs, etc. Especially intended for industry and embedded or built-in.
- Performance has been greatly optimized in its design, which is why it reaches those marks in the benchmark. This CPU can execute the RV32 instruction set as I said, both the modular extension I and E, which makes it suitable for general purpose applications.
- It also has other integrated RISC-V modules or extensions, such as M to improve multiplication and division operations, extension A to support atomic accesses for concurrency in RTOS-based systems, extension C that offers compatibility with compressed instructions 16-bit to save memory space, and also B, which provides advanced bit manipulation capabilities.
- On the other hand, great care has also been taken for efficiency, not just performance, making it ideal for low-consumption applications.
- A Stack Monitor Register system has been integrated, which prevents stack memory overflows, therefore, by avoiding these overflows you can improve the integrity of the system, which will not fail due to these problems.
- It also includes a Dynamic Branch Prediction Unit, which will improve code execution.
- Of course, it includes a JTAG debugging interface, for efficient, complete and fast debugging, making life much easier for developers.
- On the other hand, it includes an ITU or Instruction Tracing Unit, to offer developers deep knowledge about the behavior of the system.
The new Renesas RISC-V CPU is also compatible with the Renesas e2 Studio IDE and with a wide variety of third-party IDEs to develop tools for this ecosystem. In addition, the chip created has been tested both in terms of performance and functions, so you have a tested final product. As for the launch, it will be launched in 2024, early. So we will see products based on these chips, which will be very interesting, and the RISC-V phenomenon seems unstoppable in the hardware world, as Linux once was on the software side...